1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of designing a semiconductor integrated circuit. More particularly, the present invention relates to a semiconductor integrated circuit designed in consideration of an IR-drop on a power-supply wiring, and a method of designing such a semiconductor integrated circuit.
2. Description of the Background Art
A large majority of semiconductor integrated circuits operate in synchronization with a clock signal externally supplied or internally generated based on an externally-supplied signal. In general, a semiconductor integrated circuit includes a plurality of flip-flops and a circuit for generating a clock signal to be supplied to each flip-flop based on a clock signal (hereinafter referred to as a clock circuit). To cause the semiconductor integrated circuit to operate accurately, it is required that the clock signal is accurately supplied to each flip-flop. Also, to reduce power consumption of the semiconductor integrated circuit, it is effective to stop supplying the clock signal to circuit blocks that are not caused to operate. For this reason, the structure of a clock circuit and the method of supplying the clock signal are recognized as being important issues in designing a semiconductor integrated circuit.
To design a logic circuit, a cell-based designing scheme is widely used, in which rectangular cells corresponding to logical elements are placed in a two-dimensional area. Particularly in the cell-based designing scheme, for the purpose of facilitating cell placement, cells having the same height (standard cells) are often used. FIG. 19 is an illustration showing layout results of a conventional semiconductor integrated circuit. In FIG. 19, rectangular areas provided with characters C each represent a single cell (standard cell). These cells are placed within a plurality of strip areas 91 provided in parallel with each other in the two-dimensional area so as to be aligned at top. Between two strip areas 91, a power-supply wiring 92 is provided for supplying power to each cell. The power-supply wiring 92 includes a power-supply wiring 92a applied with a power-supply voltage VDD and a power-supply wiring 92b applied with a ground voltage VSS. These two types of power-supply wirings 92a and 92b are alternately placed in the two-dimensional area where the strip areas 91 are arranged.
In semiconductor integrated circuits of recent years, a phenomenon called an IR-drop is particularly a problem. A power-supply wiring includes a resistance component. Therefore, when power is supplied to each cell via such a power-supply wiring, a voltage at each cell is lower than a voltage supplied from the outside of the semiconductor integrated circuit. FIG. 20 is an illustration showing a state where an IR-drop occurs. FIG. 20 shows a distribution of power-supply voltages at the respective cells included in the semiconductor integrated circuit 93 when a power-supply voltage of 3.0V is supplied via a power-supply terminal 94 to the semiconductor integrated circuit 93. Since a resistance component 96 is included in a power-supply wiring 95, even through a power-supply voltage of 3.0V is supplied from the power-supply terminal 94, a voltage at each cell included in the semiconductor integrated circuit 93 is lower than 3.0V. For example, a power-supply voltage at a cell 97 is approximately 2.7V.
The reason for such occurrence of an IR-drop is as follows. When a cell is operated to cause changes in value of an output signal from the cell, a current flows from the power-supply wiring through a terminal of a transistor included in the cell. With this, the voltage supplied from the outside of the semiconductor integrated circuit is decreased at the time of reaching the cell by an amount equivalent to the product of the flowing current and the resistance component of the power-supply wiring. Particularly when an IR-drop occurs in a power-supply voltage supplied to a cell on a clock path, a delay time at the time of a real operation of the cell on the clock path becomes different from a delay time without occurrence of an IR-drop, thereby causing a clock skew more than assumed at the time of designing the circuit. Such a clock skew may cause a malfunction of the circuit.
As schemes of placing cells included in a semiconductor integrated circuit and measures for coping with an IR-drop, various technologies are conventionally known. Of these, examples of technologies associated with the present invention are disclosed in the following documents. Japanese Patent Laid-Open Publication No. 7-14927 discloses an automatic placement designing method and apparatus in which timing analysis is performed after placement and routing and, if timing restrictions are not satisfied, a delay cell is automatically inserted, replaced, or deleted. Japanese Patent Laid-Open Publication No. 11-251439 discloses a method in which a clock buffer for supplying a clock signal to a plurality of cells is placed at a position closer to a power-supply wiring than any of the plurality of cells. Japanese Patent Laid-Open Publication No. 2002-110802 discloses a layout apparatus and method in which timing analysis and voltage-drop analysis are performed after placement and routing and, if a voltage drop is present, an additional power-supply wiring is routed between a voltage-supply I/O and an anti-voltage-drop element that is placed together with logical elements.
However, in the semiconductor integrated circuits of recent years, with the progress of microfabrication, the width of the power-supply wiring is reduced, thereby increasing a resistance per unit length of the power-supply wiring. Therefore, an IR-drop is more prone to occur. Moreover, with an increase in circuit size and a reduction in voltage, a clock skew is also more prone to occur. Therefore, in the semiconductor integrated circuits of recent years, it is required at a level higher than ever before to suppress the occurrence of a clock skew due to an IR-drop.